complete part number includes a suffix to identify operating temperature range (e- or s-) and package type (-a or -ep). always order by complete part number, e.g., a6818sep . 4 5 6 7 8 9 10 12 13 14 15 16 17 18 11 19 20 31 32 33 34 35 36 37 load supply bb v out 2 out 7 out 8 dwg. pp-029-4 out 31 out 30 out 25 23 24 25 26 27 28 29 30 serial data out blanking logic supply 39 40 serial data in strobe ground clock clk st blnk out 9 out 10 out 15 out 16 out 24 out 23 out 22 out 17 latches register register latches 2 338 out 6 out 1 out 4 out 3 out 32 1 21 22 out 20 out 18 out 14 out 19 out 21 out 11 out 12 out 13 out 5 out 29 out 28 out 27 out 26 dd v dabic-iv, 32-bit serial-input, latched source driver data sheet 26182.128a* the a6818C devices combine a 32-bit cmos shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. designed primarily to drive vacuum-fluorescent displays, the 60 v and -40 ma output ratings also allow these devices to be used in many other peripheral power driver applications. the a6818C features an increased data input rate (com- pared with the older ucn/ucq5818Cf) and a controlled output slew rate. the cmos shift register and latches allow direct interfacing with microprocessor-based systems. with a 3.3 v or 5 v logic supply, typical serial-data input rates are up to 33 mhz. a cmos serial data output permits cascade connections in applica- tions requiring additional drive lines. similar devices are available as the a6810C (10 bits) and a6812C (20 bits). the a6818C output source drivers are npn darlingtons, capable of sourcing up to 40 ma. the controlled output slew rate reduces electro- magnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. for inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a blank- ing input high. the pnp active pull-downs will sink at least 2.5 ma. two temperature ranges are available for optimum performance in commercial (suffix s-) or industrial (suffix e-) applications. package styles are provided for through-hole dip (suffix -a) or minimum-area surface-mount plcc (suffix -ep). copper lead frames, low logic- power dissipation, and low output-saturation voltages allow these devices to drive most multiplexed vacuum-fluorescent displays over the maximum operating temperature range. features controlled output slew rate high-speed data storage 60 v minimum output breakdown high data input rate pnp active pull-downs low output-saturation voltages absolute maximum ratings at t a = 25 c logic supply voltage, v dd ................... 7.0 v driver supply voltage, v bb ................... 60 v continuous output current range, i out ......................... -40 ma to +15 ma input voltage range, v in ....................... -0.3 v to v dd + 0.3 v package power dissipation, p d ........................................ see graph operating temperature range, t a (suffix ?) .................. -40 c to +85 c (suffix ?) .................. -20 c to +85 c storage temperature range, t s ............................... -55 c to +125 c caution: these cmos devices have input static protection (class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. a6818xa 6818 low-power cmos logic and latches improved replacements for sn75518n, sn75518nf, ucn5818? and ucq5818
6818 32-bit serial-input, latched source driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 copyright ?1998, 2003 allegro microsystems, inc. a6818xep typical output driver typical input circuit 50 75 100 125 150 2.5 0.5 0 allowable package power dissipation in watts ambient temperature in c 2.0 1.5 1.0 25 dwg. gp-025b 3.0 suffix 'ep', r ja = 54 c/w suffix 'a', r ja = 36 c/w dwg. ep-010-5 in v dd v bb dwg. ep-021-19 out n 4 5 6 7 8 9 10 11 2 3 dd v bb load supply serial data in logic supply out 30 nc 44 1 serial data out 12 out 1 2 out 8 out 29 out 36 37 38 39 19 34 35 out 4 out 13 32 33 29 30 31 nc 18 19 20 21 22 st clk out 16 out 17 clock strobe ground blanking 23 24 out 15 25 26 dwg. pp-059-2 out 14 27 28 nc out 18 nc blnk 13 14 15 16 17 out 42 43 v 40 41 out 3 out 2 out 32 out 31 register latches latches register 19
6818 32-bit serial-input, latched source driver www.allegromicro.com functional block diagram truth table serial shift register contents serial latch contents output contents data clock data strobe input input i 1 i 2 i 3 ... i n-1 i n output input i 1 i 2 i 3 ... i n-1 i n blanklng i 1 i 2 i 3 ... i n-1 i n hhr 1 r 2 ... r n-2 r n-1 r n-1 llr 1 r 2 ... r n-2 r n-1 r n-1 xr 1 r 2 r 3 ... r n-1 r n r n xxx...x x x l r 1 r 2 r 3 ... r n-1 r n p 1 p 2 p 3 ... p n-1 p n p n hp 1 p 2 p 3 ... p n-1 p n lp 1 p 2 p 3 ... p n-1 p n x x x ... x x h l l l ... l l l = low logic level h = high logic level x = irrelevant p = present state r = previous state mos bipolar out 1 out 2 ground dwg. fp-013-1 out 3 out n clock serial data in strobe blanking serial data out serial-parallel shift register latches v dd v bb logic supply load supply
6818 32-bit serial-input, latched source driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 electrical characteristics at t a = +25 c (a6818s-) or over operating temperature range (a6818e- and a6818k-), v bb = 60 v unless otherwise noted. limits @ v dd = 3.3 v limits @ v dd = 5 v characteristic symbol test conditions mln. typ. max. min. typ. max. units output leakage current i cex v out = 0 v <-0.1 -15 <-0.1 -15 a output voltage v out(1) i out = -25 ma 57.5 58.3 57.5 58.3 v v out(0) i out = 1 ma 1.0 1.5 1.0 1.5 v output pull-down current i out(0) v out = 5 v to v bb 2.5 5.0 2.5 5.0 ma input voltage v in(1) 2.2 3.3 v v in(0) 1.1 1.7 v input current i in(1) v in = v dd <0.01 1.0 <0.01 1.0 a i in(0) v in = 0.8 v <-0.01 -1.0 <-0.01 -1.0 a input clamp voltage v ik i in = -200 a -0.8 -1.5 -0.8 -1.5 v serial data output voltage v out(1) i out = -200 a 2.8 3.05 4.5 4.75 v v out(0) i out = 200 a 0.15 0.3 0.15 0.3 v maximum clock frequency f c 10 33 10 33 mhz logic supply current i dd(1) all outputs high 0.25 0.75 0.3 1.0 ma i dd(0) all outputs low 0.25 0.75 0.3 1.0 ma load supply current i bb(1) all outputs high, no load 4.5 9.0 4.5 9.0 ma i bb(0) all outputs low 0.2 20 0.2 20 a blanking -to- output delay t dis(bq) c l = 30 pf, 50% to 50% 0.7 2.0 0.7 2.0 s t en(bq) c l = 30 pf, 50% to 50% 1.8 3.0 1.8 3.0 s strobe -to- output delay t p(sth-ql) r l = 2.3 k ? , c l 30 pf 0.7 2.0 0.7 2.0 s t p(sth-qh) r l = 2.3 k ? , c l 30 pf 1.8 3.0 1.8 3.0 s output fall time t f r l = 2.3 k ? , c l 30 pf 2.4 12 2.4 12 s output rise time t r r l = 2.3 k ? , c l 30 pf 2.4 12 2.4 12 s output slew rate dv/dt r l = 2.3 k ? , c l 30 pf 4.0 20 4.0 20 v/ s clock -to- serial data out delay t p(ch-sqx) i out = 200 a 50 50 ns negative current is defined as coming out of (sourcing) the specified device terminal. typical data is is for design information only and is at t a = +25 c.
6818 32-bit serial-input, latched source driver www.allegromicro.com timing requirements and specifications (logic levels are v dd and ground) serial data present at the input is transferred to the shift register on the logic 0 to logic 1 transition of the clock input pulse. on succeeding clock pulses, the registers shift data information towards the serial data output. the serial data must appear at the input prior to the rising edge of the clock input waveform. information present at any register is transferred to the respective latch when the strobe is high (serial-to-parallel conversion). the latches will continue to accept new data as long as the strobe is held high. applications where the latches are bypassed (strobe tied high) will require that the blanking input be high during serial data entry. when the blanking input is high, the output source drivers are disabled (off); the pnp active pull-down sink drivers are on. the information stored in the latches is not affected by the blanking input. with the blanking input low, the outputs are controlled by the state of their respective latches. clock serial data in strobe blanking out n dwg. wp-029 50% serial data out data data 10% 90% 50% 50% 50% c a b d e low = all outputs enabled p(sth-ql) t p(ch-sqx) t data p(sth-qh) t blanking out n dwg. wp-030a data 10% 50% en(bq) t dis(bq) t high = all outputs blanked (disabled) r t f t 50% 90% a. data active time before clock pulse (data set-up time), t su(d) ......................................... 25 ns b. data active time after clock pulse (data hold time), t h(d) ............................................... 25 ns c. clock pulse width, t w(ch) ............................................... 50 ns d. time between clock activation and strobe, t su(c) ....... 100 ns e. strobe pulse width, t w(sth) ............................................. 50 ns note ?timing is representative of a 10 mhz clock. signifi- cantly higher speeds are attainable.
6818 32-bit serial-input, latched source driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 40 14.73 12.32 1 2 3 6.35 max 1.77 0.77 0.39 min 0.558 0.356 0.381 0.204 15.24 bsc dwg. ma-003-40 mm 20 2.54 bsc 0.13 min 5.08 2.93 4 17.78 max 21 53.2 50.3 notes: 1. exact body and lead configuration at vendor? option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. lead thickness is measured at seating plane or below. a6818ea & a6811sa dimensions in inches (controlling dimensions) dimensions in millimeters (for reference only) 40 0.580 0.485 1 2 3 0.250 max 0.070 0.030 0.015 min 0.022 0.014 0.015 0.008 0.600 bsc dwg. ma-003-40 in 20 0.100 bsc 0.005 min 0.200 0.115 4 0.700 max 21 2.095 1.980
6818 32-bit serial-input, latched source driver www.allegromicro.com a6818eep & a6818sep dimensions in inches (controlling dimensions) dimensions in millimeters (for reference only) 18 28 dwg. ma-005-44a in 0.020 min 0.050 bsc 1 44 0.021 0.013 index area 2 6 7 17 29 39 40 0.695 0.685 0.032 0.026 0.319 0.291 0.319 0.291 0.180 0.165 0.695 0.685 0.656 0.650 0.656 0.650 dwg. ma-005-44a mm 17.65 17.40 0.51 min 4.57 4.20 17.65 17.40 16.662 16.510 1.27 bsc 0.812 0.661 1 44 0.533 0.331 index area 2 28 29 39 40 6 7 17 18 16.662 16.510 8.10 7.39 8.10 7.39 notes: 1. exact body and lead configuration at vendor? option within limits shown. 2. lead spacing tolerance is non-cumulative.
6818 32-bit serial-input, latched source driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
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